The present invention relates to a false lock detection circuit and a false lock detection method, a PLL circuit and a clock data recovery method, a communication device and a communication method, and an optical disk reproducing device and an optical disk reproducing method, and particularly to a false lock detection circuit and a false lock detection method, a PLL circuit and a clock data recovery method, a communication device and a communication method, and an optical disk reproducing device and an optical disk reproducing method that can detect a false lock accurately when the false lock occurs regardless of whether a ratio of data rate to clock frequency is 1:n (n is a positive integer other than one) or m:n (m is a positive integer other than one).
In the past, for example, a communication device or the like without a signal used exclusively for a clock uses a clock data recovery circuit using a PLL (Phase Locked Loop) circuit.
A clock data recovery circuit using a PLL circuit generally uses a VCO (Voltage Controlled Oscillator). By pulling in a pattern in a fixed period included in a received signal, a clock synchronous with the pattern can be generated. The VCO can lock data within a frequency variable range.
However, due to various factors, the PLL circuit may operate erroneously to lock clock frequency to a frequency different from a data rate, that is, the PLL circuit may stabilize at a frequency different from the data rate. Thus locking the clock frequency to a frequency different from the data rate is referred to as a false lock or a harmonic lock.
When a reproduced clock is normally locked to data, the data and the clock have a phase relation as shown in FIG. 1. Specifically, a rising edge of the reproduced clock is positioned at a center of each data bit, and each data bit is captured at the rising edge, whereby the data can be extracted again. On the other hand, when the reproduced clock is locked to a clock frequency where a ratio of a data rate to the clock frequency is 1:2, the data and the clock have a phase relation as shown in FIG. 2. When the reproduced clock is locked to a clock frequency where the ratio of the data rate to the clock frequency is 3:4, the data and the clock have a phase relation as shown in FIG. 3. However, when the reproduced clock is locked to the clock frequency where the ratio of the data rate to the clock frequency is 1:2, or when the reproduced clock is locked to the clock frequency where the ratio of the data rate to the clock frequency is 3:4, that is, when a false lock has occurred, a general phase comparator cannot go out of such phase relations, thus resulting in erroneous operation.
When a false lock has occurred, the clock data recovery circuit needs to be restarted to perform a new pull-in operation so that a reproduced clock is locked to data at a correct frequency.
Accordingly, a CRC (Cyclic Redundancy Check or Cyclic Redundancy Code) included in data to detect errors is used in the past. When a CRC error occurs, the clock data recovery circuit is restarted assuming that there is a possibility of occurrence of a false lock in the PLL circuit. Once locked normally, the PLL circuit hardly goes thereafter into a false lock state or an unstable state. It is therefore better to avoid restarting the PLL circuit locked normally if possible. When a CRC error occurs, however, whether the CRC error is caused by abnormal operation of the PLL or whether the CRC error is caused by a defect in the signal while the PLL is operating correctly cannot be determined.
On the other hand, there is a technique that can detect that a PLL is not normally locked when an (n+1)T or (n−1)T pattern is detected in patterns of a fixed period nT included in an input signal, for example, as shown in Japanese Patent Laid-Open No. Hei 4-132048.
When the PLL is normally locked, and data captured by the synchronous clock is random data, a probability of occurrence of data (1, 0, 1) or data (0, 1, 0) is 25%. On the other hand, as shown in FIG. 2, when a false lock has occurred at a clock frequency where a ratio of a data rate to the clock frequency is 1:n, the probability of occurrence of the data (1, 0, 1) or the data (0, 1, 0) in the data captured by the synchronous clock is 0%. Hence, on the basis of the probability of occurrence of the data (1, 0, 1) or the data (0, 1, 0), occurrence of a false lock at a clock frequency where the ratio of the data rate to the clock frequency is 1:n (n is a positive integer other than one) can be detected.